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D at a Sh ee t , V 1. 0 , Ma y 20 0 7
TDA7100
434 M Hz ASK/ FS K Transm i tte r in 10 -p in Package
W i re l e s s C o n t r o l Co mpo ne nts
Never stop thinking.
Edition 2007-05-02 Published by Infineon Technologies AG, Am Campeon 1-12, 85579 Neubiberg, Germany (c) Infineon Technologies AG 2007-05-02. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or the Infineon Technologies Companies and our Infineon Technologies Representatives worldwide (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
D at a Sh ee t , V 1. 0 , Ma y 20 0 7
TDA7100
434 M Hz ASK/ FS K Transm i tte r in 10 -p in Package
W i re l e s s C o n t r o l Co mpo ne nts
Never stop thinking.
TDA7100 Revision History: Previous Version: Page 2007-05-02 none V 1.0
Subjects (major changes since last revision)
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TDA7100
Table of Contents 1 1.1 1.2 1.3 2 2.1 2.2 2.3 2.4 2.4.1 2.4.2 2.4.3 2.4.4 2.4.4.1 2.4.4.2 2.4.4.3 2.4.4.4 2.4.5 3 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4 4.1 4.1.1 4.2 4.3 4.3.1 4.3.2 5
Page 6 6 6 6
Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin Definition and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Functional Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 PLL Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Power Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 PLL Enable Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Transmit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Power mode control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Recommended Timing Diagrams for ASK- and FSK-Modulation . . . . . 17 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Ohm-Output Testboard Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Ohm-Output Testboard Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bill of Material (50 Ohm-Output Evalboard) . . . . . . . . . . . . . . . . . . . . . . . . Stripline-Antenna Testboard Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . Stripline-Antenna Testboard Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bill of Material (Antenna board) FSK modulation . . . . . . . . . . . . . . . . . . . . Application Hints on the Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . Design Hints on the Clock Output (CLKOUT) . . . . . . . . . . . . . . . . . . . . . . Application Hints on the Power-Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC/DC Characteristic at 3V, 25C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC/DC Characteristic at 2.1V ...4.0 V, -20C ...+70C . . . . . . . . . . . . . 19 19 20 21 23 24 25 26 28 29 32 32 32 33 33 33 35
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Data Sheet
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TDA7100
Product Description
1
1.1
Product Description
Overview
The TDA7100 is a single chip ASK/FSK transmitter for operation in the frequency band 433-435 MHz. The IC offers a high level of integration and needs only a few external components. The device contains a fully integrated PLL synthesizer and a high efficiency power amplifier to drive a loop antenna. A special circuit design and an unique power amplifier design are used to save current consumption and therefore to save battery life. Additional features are a power down mode and a divided clock output.
1.2
* * * * * * * * * * * * *
Features
fully integrated frequency synthesizer VCO without external components ASK and FSK modulation frequency range 433-435 MHz high efficiency power amplifier (typically 5 dBm) low supply current voltage supply range 2.1 ... 4 V temperature range -20 ... +70C power down mode crystal oscillator 13.56 MHz FSK-switch divided clock output for C low external component count
1.3
* * *
Application
Remote control systems Alarm systems Communication systems
Table 1 Type TDA7100
Order Information Ordering Code SP000296466 Package PG-TSSOP-10
available on tape and reel
Data Sheet
6
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TDA7100
Functional Description
2
2.1
Functional Description
Pin Configuration
CLKOUT VS GND FSKOUT COSC
1 2 3 4 5
10 9
PDWN PAOUT PAGND FSKDTA ASKDTA
TDA 7100
8 7 6
Figure 1
IC Pin Configuration
2.2
Table 2 Pin No. 1 2 3 4 5 6 7 8 9 10
Pin Definition and Functions
Pin Definition and Functions - Overview Symbol CLKOUT VS GND FSKOUT COSC ASKDTA FSKDTA PAGND PAOUT PDWN Function Clock Driver Output (847.5 kHz) Voltage Supply Ground Frequency Shift Keying Switch Output Crystal Oscillator Input (13.56 MHz) Amplitude Shift Keying Data Input Frequency Shift Keying Data Input Power Amplifier Ground Power Amplifier Output (434 MHz) Power Down Mode Control
Data Sheet
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TDA7100
Functional Description
Table 3 Pin No. 1
Pin Definition and Function1) Interface Schematic Function Clock output to supply an external device. An external pull-up resistor has to be added in accordance to the driving requirements of the external device. The clock frequency is 847.5 kHz.
Symbol CLKOUT
VS 1 300
2
VS
This pin is the positive supply of the transmitter electronics. An RF bypass capacitor should be connected directly to this pin and returned to GND (pin 3) as short as possible. General ground connection.
VS VS
3 4
GND FSKOUT
This pin is connected to a switch to GND (pin 3). The switch is closed when the signal at FSKDTA (pin 7) is in a logic low state.
4
200 A
120 k
200 k
The switch is open when the signal at FSKDTA (pin 7) is in a logic high state. FSKOUT can switch an additional capacitor to the reference crystal network to pull the crystal frequency by an amount resulting in the desired FSK frequency shift of the transmitter output frequency.
Data Sheet
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TDA7100
Functional Description Pin No. 5 Symbol COSC
VS 6 k 5 VS
Interface Schematic
Function This pin is connected to the reference oscillator circuit. The reference oscillator is working as a negative impedance converter. It presents a negative resistance in series to an inductance at the COSC pin.
100 A
6
ASKDTA
VS +1.2 V
Digital amplitude modulation can be imparted to the Power Amplifier through this pin. A logic high (ASKDTA > 1.5 V or open) enables the Power Amplifier. A logic low (ASKDTA < 0.5 V) disables the Power Amplifier.
60 k 6 +1.1 V 90 k 50 pF 30 A
Data Sheet
9
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TDA7100
Functional Description Pin No. 7 Symbol FSKDTA
VS +1.2 V
Interface Schematic
Function Digital frequency modulation can be imparted to the Xtal Oscillator by this pin. The VCO-frequency varies in accordance to the frequency of the reference +1.1 V oscillator.
30 A
60 k 7 90 k
A logic high (FSKDTA > 1.5V or open) sets the FSK switch to a high impedance state. A logic low (FSKDTA < 0.5 V) closes the FSK switch from FSKOUT (pin 4) to GND (pin 3). A capacitor can be switched to the reference crystal network this way. The Xtal Oscillator frequency will be shifted giving the designed FSK frequency deviation.
Data Sheet
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TDA7100
Functional Description Pin No. 8 Symbol PAGND
9
Interface Schematic
Function Ground connection of the power amplifier. The RF ground return path of the power amplifier output PAOUT (pin 9) has to be concentrated to this pin. RF output pin of the transmitter. A DC path to the positive supply VS has to be supplied by the antenna matching network. Disable pin for the complete transmitter circuit.
9
PAOUT
8
10
PDWN
VS 40 A (ASKDTA+FSKDTA)
A logic low (PDWN < 0.7 V) turns off all transmitter functions. A logic high (PDWN > 1.5 V) gives access to all transmitter functions. PDWN input will be pulled up by 40 A internally by either setting FSKDTA or ASKDTA to a logic high-state.
5 k 10 "ON" 150 k
250 k
1) Indicated voltages and currents apply for PLL Enable Mode and Transmit Mode. In Power Down Mode, the values are zero or high-ohmic.
Data Sheet
11
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2.3
Figure 2
Data Sheet
FSK Data Input ASK Data Input Power Down Control Power Supply VS
7 6 10 2
OR On PFD :64 VCO :2 Power AMP
Functional Block Diagram
Functional Block Diagram
Power Supply 9
FSK Switch
4
12
:16 LF 1 3
Ground
Crystal 13.56 MHz
5
XTAL Osc
Power Amplifier Output
8
Power Amplifier Ground
Functional Description
Clock Output
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TDA7100
TDA7100
Functional Description
2.4 2.4.1
Functional Block Description PLL Synthesizer
The Phase Locked Loop synthesizer consists of a Voltage Controlled Oscillator (VCO), an asynchronous divider chain, a phase detector, a charge pump and a loop filter. It is fully implemented on chip. The tuning circuit of the VCO consisting of spiral inductors and varactor diodes is on chip, too. Therefore no additional external components are necessary. The nominal center frequency of the VCO is 868 MHz. The oscillator signal is fed both, to the synthesizer divider chain and to the power amplifier. The overall division ratio of the asynchronous divider chain is 64. The phase detector is a Type IV PD with charge pump. The passive loop filter is realized on chip.
2.4.2
Crystal Oscillator
The crystal oscillator operates at 13.56 MHz. The crystal frequency is divided by 16. The resulting 847.5 kHz are available at the clock output CLKOUT (pin1) to drive the clock input of a micro controller. To achieve FSK transmission, the oscillator frequency can be detuned by a fixed amount by switching an external capacitor via FSKOUT (pin 4). The condition of the switch is controlled by the signal at FSKDTA (pin 7). Table 4
1)
FSKDTA - FSK Switch FSK Switch CLOSED OPEN Voltage at pin < 0.5V Pin open Voltage at pin > 1.5V
FSKDTA (pin7) Low Open2), High3) 1) Low: 2) Open: 3) High:
2.4.3
Power Amplifier
The VCO frequency is divided by 2 and fed to the Power Amplifier. The Power Amplifier can be switched on and off by the signal at ASKDTA (pin 6).
Data Sheet
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TDA7100
Functional Description
Table 5
1) 2) 3)
ASKDTA - Power Amplifier Power Amplifier OFF ON Voltage at pin < 0.5V Pin open Voltage at pin > 1.5V
ASKDTA (pin6) Low Open , High 1) Low: 2) Open: 3) High:
The Power Amplifier has an Open Collector output at PAOUT (pin 9) and requires an external pull-up coil to provide bias. The coil is part of the tuning and matching LC circuitry to get best performance with the external loop antenna. To achieve the best power amplifier efficiency, the high frequency voltage swing at PAOUT (pin 9) should be twice the supply voltage. The power amplifier has its own ground pin PAGND (pin 8) in order to reduce the amount of coupling to the other circuits.
2.4.4
Power Modes
The IC provides three power modes, the POWER DOWN MODE, the PLL ENABLE MODE and the TRANSMIT MODE.
2.4.4.1
Power Down Mode
In the POWER DOWN MODE the complete chip is switched off. The current consumption is typically 0.3 nA at 3 V 25C. The value is typically 5nA at 70C.
2.4.4.2
PLL Enable Mode
In the PLL ENABLE MODE the PLL is switched on but the power amplifier is turned off to avoid undesired power radiation during the time the PLL needs to settle. The turn on time of the PLL is determined mainly by the turn on time of the crystal oscillator and is less than 1 msec when the specified crystal is used. The current consumption is typically 3.5 mA.
Data Sheet
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TDA7100
Functional Description
2.4.4.3
Transmit Mode
In the TRANSMIT MODE the PLL is switched on and the power amplifier is turned on too. The current consumption of the IC is typically 7 mA when using a proper transforming network at PAOUT, see Figure 8.
2.4.4.4
Power mode control
The bias circuitry is powered up via a voltage V > 1.5 V at the pin PDWN (pin10). When the bias circuitry is powered up, the pins ASKDTA and FSKDTA are pulled up internally. Forcing the voltage at the pins low overrides the internally set state. Alternatively, if the voltage at ASKDTA or FSKDTA is forced high externally, the PDWN pin is pulled up internally via a current source. In this case, it is not necessary to connect the PDWN pin, it is recommended to leave it open. The principle schematic of the power mode control circuitry is shown in Figure 3
PDWN ASKDTA FSKDTA
On
OR
Bias Source 120 k
Bias Voltage
120 k
On
FSK
FSKOUT PAOUT
PLL
434 MHz
PA IC
Figure 3
Power mode control circuitry
Data Sheet
15
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TDA7100
Functional Description Table 6 provides a listing of how to get into the different power modes Table 6 PDWN Low
1) 2)
Power Modes FSKDTA Low, Open Low Low, Open, High High Low, Open, High High Low, Open, High ASKDTA Low, Open Low Low Low Open, High Open, High High TRANSMIT PLL ENABLE MODE POWER DOWN
Open Open High Open Open
High3)
1) Low: 2) Open: 3) High:
Voltage at pin < 0.7V (PDWN) Voltage at pin < 0.5V (FSKDTA, ASKDTA) Pin open Voltage at pin > 1.5V
Other combinations of the control pins PDWN, FSKDTA and ASKDTA are not recommended.
Data Sheet
16
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TDA7100
Functional Description
2.4.5
Recommended Timing Diagrams for ASK- and FSK-Modulation
ASK Modulation using FSKDTA and ASKDTA, PDWN not connected
Modes:
Power Down
PLL Enable
Transmit
High
FSKDTA
Low
to t
DATA Open, High
ASKDTA
Low
to t
min. 1 msec.
Figure 4
ASK Modulation
FSK Modulation using FSKDTA and ASKDTA, PDWN not connected.
Modes:
Power Down
PLL Enable
Transmit DATA
High
FSKDTA
Low
to t
High
ASKDTA
Low
to t
min. 1 msec.
Figure 5
FSK Modulation
Data Sheet
17
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TDA7100
Functional Description
Alternative ASK Modulation, FSKDTA not connected.
Modes: Power Down PLL Enable Transmit
High
PDWN
Low
to t
DATA Open, High
ASKDTA
Low
to t
min. 1 msec.
Figure 6
Alternative ASK Modulation
Alternative FSK Modulation
Modes: Power Down PLL Enable Transmit
High
PDWN
Low Open, High
to t
ASKDTA
Low Open, High
to t
DATA
FSKDTA
Low
to t
min. 1 msec.
Figure 7
Alternative FSK Modulation
Data Sheet
18
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TDA7100
Applications
3
3.1
Applications
50 Ohm-Output Testboard Schematic
Figure 8
Data Sheet
50 Ohm-output testboard schematic
19 V 1.0, 2007-05-02
TDA7100
Applications
3.2
50 Ohm-Output Testboard Layout
Figure 9
Top Side of TDA7100-Testboard with 50 Ohm-Output
Figure 10
Bottom Side of TDA7100-Testboard with 50 Ohm-Output
Data Sheet
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TDA7100
Applications
3.3
Table 7 Ref.
R1 R2 R3 R4 R5 R6 R7 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 L1 L2
Bill of Material (50 Ohm-Output Evalboard)
Bill of Materials (cont'd) Value
open open 4k7 12k open 15k open 10p 6p8 open open 100p 12p 39p 330p 3p3 47n 47n 120n 0603, X7R, +/-10% 0603, C0G, +/-1% 0603, C0G, +/-1% 0603, C0G, +/-5% 0603, C0G, +/-0.1p 0603, X7R, +/-10% EPCOS SIMID 0603-C, +/-2% EPCOS SIMID 0603-C, +/-2% 0603, C0G, +/-1% 0603, C0G, +/-0.1p 0603, +/-5% 0603, +/-5% 0603, +/-5%
Specification
Data Sheet
21
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TDA7100
Applications Ref.
X1 X2 X3 X4 X5 X6 X7 JP1 JP2 Q1 IC1
Value
n.e. n.e. Pin Pin SMA-connector SMA-connector n.e. solder bridge solder bridge 13.56875 MHz TDA7100
Specification
single-pole connector, 2.54mm single-pole connector, 2.54mm
in position "XTAL" in position "FSK" Tokyo Denpa TSS-3B 13.56875 MHz Spec.No. 10-50205
Data Sheet
22
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TDA7100
Applications
3.4
Stripline-Antenna Testboard Schematic
Figure 11
Stripline-antenna testboard schematic
Data Sheet
23
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TDA7100
Applications
3.5
Stripline-Antenna Testboard Layout
TDA7100
Figure 12
Top Side of TDA7100-Testboard with Stripline-Antenna
Figure 13
Bottom Side of TDA7100-Testboard with Stripline-Antenna
Please note that this board layout may be used for both high- and low-power applications, see also the bill of materials on the subsequent pages. In case of ASK operation the solder bridge JP2 has to be shortened in the "ASK"position, in case of FSK modulation in the"FSK" position. Solder bridge JP1between C1, C2 and C3) gives a choice of operating the board with the on-board crystal as reference ("XTAL" shortened, i.e. close to C1 and C2) or with an external clock generator (solder bridge shorts pads between C3 and C2).
Data Sheet 24 V 1.0, 2007-05-02
TDA7100
Applications
3.6
Table 8 Ref.
R1 R2 R3 R4 R5 R6 R7 R8 R9 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 L1 L2 X1 X3 X4 S1 JP1 JP2 Q1
Bill of Material (Antenna board) FSK modulation
Bill of Materials (cont'd) Value
open 0R 0R 82k open open 100n 39R 15k 10p 6p8 open open open 10n 5p6 open 4p7 47n 100n 0R n.e. n.e. n.e. push-button solder bridge solder bridge 13.56875 MHz STTSKHMPW, ALPS in position "XTAL" in position "FSK" Tokyo Denpa TSS-3B 13.56875 MHz Spec.No. 10-50205
25 V 1.0, 2007-05-02
Specification
0603, SMD-Jumper 0603, SMD-Jumper 0603, +/-5%
0603, X7R, +/-10% 0603, +/-1% 0603, +/-5% 0603, C0G, +/-1% 0603, C0G, +/-0.1p
0603, X7R, +/-10% 0603, C0G, +/-0.1p 0603, C0G, +/-0.1p 0603, X7R, +/-10% 0603, EPCOS SIMID, +/-2% 0603, SMD-Jumper
Data Sheet
TDA7100
Applications Ref.
IC1 IC2 BAT1
Value
TDA7100 HCS360 battery holder battery
Specification
P-TSSOP-10 SO8 HU2031-1, Renata CR2032, Renata
3.7
Application Hints on the Crystal Oscillator
The crystal oscillator achieves a turn on time less than 1 msec when the specified crystal is used. To achieve this, a NIC oscillator type is implemented in the TDA7100. The input impedance of this oscillator is a negative resistance in series to an inductance. Therefore the load capacitance of the crystal CL (specified by the crystal supplier) is transformed to the capacitance Cv.
-R
L
f, CL Cv
IC
Figure 14
Formula 1:
Application Hints
Cv =
1 1 + 2L CL
CL: : L:
crystal load capacitance for nominal frequency angular frequency inductance of the crystal oscillator
Data Sheet
26
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TDA7100
Applications Example for the ASK-Mode:
Referring to the application circuit, in ASK-Mode the capacitance C2 is replaced by a short to ground. Assume a crystal frequency of 13.56MHz and a crystal load capacitance of CL = 12 pF. The inductance L at 13.56MHz is about 4.6 H. Therefore C1 is calculated to 10 pF.
Cv =
1 1 + 2L CL
= C1
Example for the FSK-Mode:
FSK modulation is achieved by switching the load capacitance of the crystal as shown below.
FSKDTA
FSKOUT
Csw -R L
COSC
f, CL Cv1
Cv2
IC
Figure 15
FSK Mode
The frequency deviation of the crystal oscillator is multiplied with the divider factor N of the Phase Locked Loop to the output of the power amplifier. In case of small frequency deviations (up to +/- 1000 ppm), the two desired load capacitances can be calculated with the formula below.
CL =
CL m C 0
f 2(C 0 + CL ) (1 + ) N * f1 C1 f 2(C 0 + CL ) 1 (1 + ) N * f1 C1
27 V 1.0, 2007-05-02
Data Sheet
TDA7100
Applications
CL: C0: f: : N: df: crystal load capacitance for nominal frequency shunt capacitance of the crystal frequency = 2f: angular frequency division ratio of the PLL peak frequency deviation
Because of the inductive part of the TDA7100, these values must be corrected by Formula 1 on the preceding page. The value of Cv can be calculated.
Cv =
1 1 + 2L CL
If the FSK switch is closed, Cv- is equal to Cv1 (C1 in the application diagram). If the FSK switch is open, Cv2 (C2 in the application diagram) can be calculated. Csw Cv1 - (Cv + ) (Cv1 + Csw ) (Cv + ) - Cv1
Cv 2 = C 2 = Csw:
parallel capacitance of the FSK switch (3 pF incl. layout parasitics)
Remark: These calculations are only approximations. The necessary values depend on the layout also and must be adapted for the specific application board.
3.8
Design Hints on the Clock Output (CLKOUT)
The CLKOUT pin is an open collector output. An external pull up resistor (RL) should be connected between this pin and the positive supply voltage. The value of RL is
Data Sheet
28
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TDA7100
Applications
depending on the clock frequency and the load capacitance CLD (PCB board plus input capacitance of the microcontroller). RL can be calculated to:
RL =
1 fCLKOUT * 8 * CLD
Table 9
Clock Output fCLKOUT=847.5 kHz
CL[pF] 5 10 20 RL[kOhm] 27 12 6.8
Remark:
To achieve a low current consumption and a low spurious radiation, the largest possible RL should be chosen.
Even harmonics of the signal at CLKOUT can interact with the crystal oscillator input COSC preventing the start-up of oscillation. Care must be taken in layout by sufficient separation of the signal lines to ensure sufficiently small coupling.
3.9
Application Hints on the Power-Amplifier
The power amplifier operates in a high efficient class C mode. This mode is characterized by a pulsed operation of the power amplifier transistor at a current flow angle of <<. A frequency selective network at the amplifier output passes the fundamental frequency component of the pulse spectrum of the collector current to the load. The load and its resonance transformation to the collector of the power amplifier can be generalized by the equivalent circuit of Figure 16. The tank circuit L//C//RL in parallel to the output impedance of the transistor should be in resonance at the operating frequency of the transmitter.
Data Sheet
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TDA7100
Applications
VS L C RL
Figure 16
Equivalent power amplifier tank circuit
The optimum load at the collector of the power amplifier for "critical" operation under idealized conditions at resonance is:
R LC =
V S2 2 * PO
The theoretical value of RLC for an RF output power of Po= 5 dBm (3.16 mW) is:
R LC =
32 = 1423 2 * 0 .00316
"Critical" operation is characterized by the RF peak voltage swing at the collector of the PA transistor to just reach the supply voltage VS. The high degree of efficiency under "critical" operating conditions can be explained by the low power losses at the transistor. During the conducting phase of the transistor, its collector voltage is very small. This way the power loss of the transistor, equal to iC*uCE is minimized. This is particularly true for small current flow angles of <<. In practice the RF-saturation voltage of the PA transistor and other parasitics reduce the "critical" RLC. The output power Po is reduced by operating in an "overcritical" mode characterised by RL > RLC. The power efficiency (and the bandwidth) increase when operating at a slightly higher RL, as shown in Figure 17. The collector efficiency E is defined as
E=
PO VS I C
The diagram of Figure 17 was measured directly at the PA-output at VS = 3 V. Losses in the matching circuitry decrease the output power by about 1.5 dB. As can be seen from
Data Sheet
30
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TDA7100
Applications
the diagram, 550 is the optimum impedance for operation at 3 V. For an approximation of ROPT and POUT at other supply voltages those two formulas can be used:
ROPT ~ VS
and
POUT ~ ROPT
10*E Po [mW] 7 6 5 4 3 2 1 0 0 1000 2000 3000 RL [Ohm]
10*E Po
Figure 17
Output power Po (mW) and collector efficiency E vs. load resistor RL.
The DC collector current Ic of the power amplifier and the RF output power Po vary with the load resistor RL. This is typical for overcritical operation of class C amplifiers. The collector current will show a characteristic dip at the resonance frequency for this type of "overcritical" operation. The depth of this dip will increase with higher values of RL.
Data Sheet
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TDA7100
Reference
4
4.1 4.1.1
Reference
Electrical Data Absolute Maximum Ratings
Attention: The maximum ratings must not be exceeded under any circumstances, not even momentarily and individually, as permanent damage to the IC will result.
Table 10 Parameter
Absolute Maximum Ratings, Tamb = -20 C ... +70 C Symbol
TJ Ts RthJA VS Vpins Vpin9 VESD VESD -0.3 -0.3 -0.3 -1 -2
Limit Values min. max.
+150 +125 220 +4.0 VS + 0.3 2 * VS +1 +2 -40 -40
Unit
C C K/W V V V kV kV
Remarks
Junction Temperature Storage Temperature Thermal Resistance Supply voltage Voltage at any pin excluding pin 9 Voltage at pin 9 ESD integrity, all pins ESD integrity, all pins excluding pin 9
No ESD-Diode to VS JEDEC Standard JESD22-A114-B JEDEC Standard JESD22-A114-B
Ambient Temperature under bias: TA = -20C to +70C Note: All voltages referred to ground (pins) unless stated otherwise. Pins 3 and 8 are grounded.
Data Sheet
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TDA7100
Reference
4.2
Operating Ratings
Within the operational range the IC operates as described in the circuit description.
Table 11 Parameter
Operating Ratings Symbol
VS TA 2.1 -20
Limit Values min. max.
4.0 70
Unit
V C
Test Conditions
Supply voltage Ambient temperature
4.3
AC/DC Characteristics
AC/DC characteristics involve the spread of values guaranteed within the specified supply voltage and ambient temperature. Typical charcateristics are the median of the production.
4.3.1
Table 12
AC/DC Characteristic at 3V, 25C
Supply Voltage VS=3V, Ambient temperature Tamb=25C Symbol min. Limit Values typ.
0.3
Parameter Current consumption
Power Down mode
max.
100
Unit Test Conditions
nA V (Pins 10, 6 and 7) < 0.2 V
IS PDWN
PLL Enable mode Transmit mode 434 MHz
IS PLL_EN IS TRANSM
3.5 7.5
4.2
mA mA
Output frequency
Output frequency Output current (High) Saturation Voltage (Low)1) fOUT ICLKOUT VSATL 427 434 442 5 0.56 MHz fOUT = 32 * fCOSC A V VCLKOUT = VS ICLKOUT = 1 mA
Clock Driver Output (Pin 1)
Data Sheet
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TDA7100
Reference Table 12 Parameter Supply Voltage VS=3V, Ambient temperature Tamb=25C (cont'd) Symbol min. FSK Switch Output (Pin 4)
On resistance On capacitance Off resistance Off capacitance Load capacitance Serial Resistance of the crystal Input inductance of the COSC pin 4.6 RFSKOUT CFSKOUT RFSKOUT 10 CFSKOUT CCOSCmax 1.5 5 100 250 6 pF k pF pF H f = 13.56 MHz f = 13.56 MHz VFSKDTA = 0 V VFSKDTA = 0 V VFSKDTA = VS VFSKDTA = VS
Limit Values typ. max.
Unit Test Conditions
Crystal Oscillator Input (Pin 5)
ASK Modulation Data Input (Pin 6)
ASK Transmit disabled VASKDTA 0 ASK Transmit enabled VASKDTA 1.5 Input bias current ASKDTA Input bias current ASKDTA ASK data rate FSK Switch on FSK Switch off Input bias current FSKDTA Input bias current FSKDTA FSK data rate Output Power2) at 434 MHz transformed to 50 Ohm
Data Sheet
0.5 VS 30
V V A A VASKDTA = VS VASKDTA = 0 V
IASKDTA IASKDTA fASKDTA VFSKDTA 0 VFSKDTA 1.5 IFSKDTA IFSKDTA fFSKDTA POUT434 5.2 -20 -20
20 0.5 VS 30
kHz V V A A VFSKDTA = VS VFSKDTA = 0 V
FSK Modulation Data Input (Pin 7)
20
kHz dBm
Power Amplifier Output (Pin 9)
34
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TDA7100
Reference Table 12 Parameter Supply Voltage VS=3V, Ambient temperature Tamb=25C (cont'd) Symbol min. Power Down Mode Control (Pin 10)
Power Down mode PLL Enable mode Transmit mode Input bias current PDWN V PDWN V PDWN V PDWN IPDWN 0 1.5 1.5 0.7 VS VS 30 V V V A VASKDTA < 0.2 V VFSKDTA < 0.2 V VASKDTA < 0.5 V VASKDTA > 1.5 V VPDWN = VS
Limit Values typ. max.
Unit Test Conditions
1) Derating linearly to a saturation voltage of max. 140 mV at ICLKOUT = 0 mA 2) Power amplifier in overcritical C-operation Matching circuitry as used in the 50 Ohm-Output Testboard at the specified frequency. Tolerances of the passive elements not taken into account.
4.3.2
Table 13
AC/DC Characteristic at 2.1V ...4.0 V, -20C ...+70C
Supply Voltage VS=2.1V ... 4.0V, Tamb=-20C ... +70C Symbol min. Limit Values typ. max.
4 3.5 7.5 432 434 437 5 0.5 4.6
Parameter Current consumption
Power Down mode PLL Enable mode Transmit mode
Unit Test Conditions
A mA mA MHz fOUT = 32 * fCOSC A V VCLKOUT = VS ICLKOUT = 0.6 mA V (Pins 10, 6 and 7) < 0.2 V
IS PDWN IS PLL_EN IS TRANSM fOUT ICLKOUT VSATL
Output frequency
Output frequency Output current (High) Saturation Voltage (Low)1)
Clock Driver Output (Pin 1)
Data Sheet
35
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TDA7100
Reference Table 13 Parameter Supply Voltage VS=2.1V ... 4.0V, Tamb=-20C ... +70C (cont'd) Symbol min. FSK Switch Output (Pin 4)
On resistance On capacitance Off resistance Off capacitance Load capacitance Serial Resistance of the crystal Input inductance of the COSC pin 4.6 RFSKOUT CFSKOUT RFSKOUT 10 CFSKOUT CCOSCmax 1.5 5 100 280 6 pF k pF pF H f = 13.56 MHz f = 13.56 MHz VFSKDTA = 0 V VFSKDTA = 0 V VFSKDTA = VS VFSKDTA = VS
Limit Values typ. max.
Unit Test Conditions
Crystal Oscillator Input (Pin 5)
ASK Modulation Data Input (Pin 6)
ASK Transmit disabled VASKDTA 0 ASK Transmit enabled VASKDTA 1.5 Input bias current ASKDTA Input bias current ASKDTA ASK data rate FSK Switch on FSK Switch off Input bias current FSKDTA Input bias current FSKDTA FSK data rate IASKDTA IASKDTA fASKDTA VFSKDTA 0 VFSKDTA 1.5 IFSKDTA IFSKDTA fFSKDTA -20 20 -20 20 0.5 VS 33 0.5 VS 33 V V A A kHz V V A A kHz VFSKDTA = VS VFSKDTA = 0 V VASKDTA = VS VASKDTA = 0 V
FSK Modulation Data Input (Pin 7)
Data Sheet
36
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TDA7100
Reference Table 13 Parameter Supply Voltage VS=2.1V ... 4.0V, Tamb=-20C ... +70C (cont'd) Symbol min. Power Amplifier Output (Pin 9)
Output Power 2) at 434 POUT, 434 MHz POUT, 434 transformed to 50 POUT, 434 Ohm. 2.5 5.2 6.9 dBm VS = 2.1 V dBm VS = 3.0 V dBm VS = 4.0 V 0.5 VS VS 38 V V V A VASKDTA < 0.2 V VFSKDTA < 0.2 V VASKDTA < 0.5 V VASKDTA > 1.5 V VPDWN = VS
Limit Values typ. max.
Unit Test Conditions
Power Down Mode Control (Pin 10)
Power Down mode PLL Enable mode Transmit mode Input bias current PDWN V PDWN V PDWN V PDWN IPDWN 0 1.5 1.5
1) Derating linearly to a saturation voltage of max. 140 mV at ICLKOUT = 0 mA 2) Matching circuitry as used in the 50 Ohm-Output Testboard. Tolerances of the passive elements not taken into account. Typ. temperature dependency at 2.1 V: +0.3 dBm@-20C and -0.5 dBm@+70C, reference +25C Typ. temperature dependency at 3.0 V: +0.35 dBm@-20C and -0.7 dBm@+70C, reference +25C Typ. temperature dependency at 4.0 V: +0.7 dBm@-20C and -1.1 dBm@+70C, reference +25C
Data Sheet
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TDA7100
Package Outlines
5
Package Outlines
1.1 max.
0.15 max.
H
A 0.22 0.05 0.08
M
0.1 A ABC
0.09
0.5
0.42 +0.15 -0.1 4.9 0.25
M
6 max.
ABC
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3 0.1
C
3 0.1 Index Marking
Figure 18
B
PG-TSSOP-10
You can find all of our packages, sorts of packing and others in our Infineon Internet Page "Products": http://www.infineon.com/products. SMD = Surface Mounted Device Data Sheet 38 Dimensions in mm
+0.08 0.125 -0.05
0.85 0.1
TDA7100
List of Figures
Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18
Page
IC Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Power mode control circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 ASK Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 FSK Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Alternative ASK Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Alternative FSK Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 50 Ohm-output testboard schematic . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Top Side of TDA7100-Testboard with 50 Ohm-Output . . . . . . . . . . . . 20 Bottom Side of TDA7100-Testboard with 50 Ohm-Output. . . . . . . . . . 20 Stripline-antenna testboard schematic. . . . . . . . . . . . . . . . . . . . . . . . . 23 Top Side of TDA7100-Testboard with Stripline-Antenna . . . . . . . . . . . 24 Bottom Side of TDA7100-Testboard with Stripline-Antenna . . . . . . . . 24 Application Hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 FSK Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Equivalent power amplifier tank circuit. . . . . . . . . . . . . . . . . . . . . . . . . 30 Output power Po (mW) and collector efficiency E vs. load resistor RL. 31 PG-TSSOP-10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Data Sheet
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TDA7100
List of Tables
Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13
Page
Order Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin Definition and Functions - Overview . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin Definition and Function1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 FSKDTA - FSK Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 ASKDTA - Power Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Bill of Materials. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Bill of Materials. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Clock Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Absolute Maximum Ratings, Tamb = -20 C ... +70 C . . . . . . . . . . . . . 32 Operating Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Supply Voltage VS=3V, Ambient temperature Tamb=25C . . . . . . . . . . 33 Supply Voltage VS=2.1V ... 4.0V, Tamb=-20C ... +70C. . . . . . . . . . . . 35
Data Sheet
40
V 1.0, 2007-05-02
www.infineon.com
Published by Infineon Technologies AG

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